External testing of digital systems involves the use of expensive testers. Built-in self-test (BIST) is a technique in which some tester functions are incorporated as part of the system so that the system can test itself. More specifically, special purpose hardware is used to generate test patterns that are applied to the circuit-under-test (CUT) and to analyze the output response. As the number of pins, speed, and complexity of integrated circuits continues to grow rapidly, BIST is becoming an increasingly important and attractive approach.
A conventional BIST approach is shown in FIG. 1. In this test-per-scan approach a linear feedback shift register (LFSR) 10 is used to generate a pseudo-random sequence of bit subsequences that are shifted directly into a scan chain 12. The bits in the scan chain 12 serve as test patterns applied to the circuit-under-test (CUT) 14. The response is loaded back into the scan chain 12 and shifted out into a signature register 16 for compaction. Meanwhile, new bits from the LFSR 10 are shifted into the scan chain 12 to serve as another test pattern. Each test pattern corresponds to a subsequence of the pseudo-random sequence generated by LFSR 10. Usually a large number of test patterns are required in order to adequately test a circuit.
Unfortunately, many circuits contain random-pattern-resistant (r.p.r.) faults which limit the fault coverage that can be achieved with this approach. Accordingly, several methods have been proposed for improving the fault coverage for a test-per-scan BIST scheme.
One solution is to modify the CUT 14 by either inserting test points or by redesigning it. These techniques generally add extra levels of logic to the circuit which may increase circuit delay and degrade system performance. Moreover, in some cases it is impossible or undesirable to modify the function logic (e.g., macrocells, cores, proprietary designs). In addition, if test points are inserted to increase the detection probabilities of the r.p.r. faults, the test points require that the function logic be modified.
Another solution is to add weighting logic to the BIST scheme in a way that biases the pseudo-random sequences towards those that detect the r.p.r. faults. This additional logic changes the probability that each bit in the pseudo-random sequence will be a 1 or a 0. The weight logic can be placed either at the input of the scan chain 12 or within the scan chain in the individual scan cells themselves. Multiple weight sets are usually required due to conflicting input values needed to detect r.p.r. faults. Because the weight sets need to be stored on-chip and control logic is required to switch between them, the hardware overhead can be large. An example of this approach is found in U.S. Pat. No. 5,612,963 to Koenenmann et al.
Another approach to improving the detection of r.p.r. faults is to use "mixed-mode" testing in which deterministic test patterns are used to detect the r.p.r. faults that the pseudo-random sequence misses. Storing deterministic patterns in a ROM, however, requires a large amount of hardware overhead. A variation on this technique that reduces the storage requirements is based on reseeding the LFSR 18 used for generating the pseudo-random sequence. A block diagram of a circuit implementing this type of approach is shown in FIG. 2. In this approach, precomputed seeds are loaded into the LFSR 18, which then generates deterministic sequences selected to improve r.p.r. fault detection. By storing a set of seeds in a ROM 20 instead of a set of deterministic patterns, the hardware overhead is reduced. Nevertheless, LFSR reseeding requires a ROM at least as large as the total number of specified bits in the set of test sequences that detect the r.p.r. faults. In addition, it requires a multi-phase test and additional reseeding control logic 22.
Other variations on the "mixed-mode" technique use a multiple-polynomial LFSR for encoding a set of deterministic test sequences. By "merging" and "concatenating" the sequences, they further reduce the number of bits that need to be stored. Even further reduction can be achieved by using variable-length seeds and a special automatic test pattern generation (ATPG) algorithm. This approach, however, still does not eliminate the need to store data in ROM. It also requires complex control logic for reseeding.